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Exam Number : C2080-474
Exam Name : IBM Tealeaf Customer Experience Management V8.7- Business Analysis
Vendor Name : IBM
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an efficient ASIP Design Methodology | C2080-474 test Questions and test Braindumps

Selim ZOGHLAMI*, Raphael DAVID*, Stéphane GUYETANT* and Daniel ETIEMBLE*** CEA record, Embedded Computing Laboratory** LRI - computer Science Lab

abstract :

The processors that are utilized in embedded methods should fulfil a set of constraints: program execution time, vigour consumption, chip size, code size etc. during this paper, they focal point on the design of software particular guideline-set processors, and greater precisely on a good methodology for the Design house Exploration of an ASIP for the audio and speech area. using this technique, they designed a high efficiency ASIP attaining over 13GOPS/mm2 with a 350MHz clock frequency in a low-vigour 65-nm TSMC know-how. The development time was lower than two man-months.

1. CONTEXT

The Design house Exploration of an ASIP (application specific instruction-set Processor) can also be very complicated as a result of the massive variety of design parameters. In their design case examine, they focus handiest on some key architectural points like the pipeline depth, the number of registers, the implementation of particular operations, the variety of guidelines that can also be executed simultaneously and so on. discovering the top-quality trade-off for the values of all these parameters is not glaring and they need a selected design methodology to fulfill all necessities.

In determine 1, they present different processes that may also be used to locate the most effective trade-off. To make the figure readable, they simplest use agree with two design parameters P1 and P2 that could be for instance pipeline depth and the variety of guidance that are carried out concurrently.

figure 1: different processes to discover the ultimate values of two design parameters

(a) The exhaustive search considers all the possible values of every parameter. Due the significant number of parameters, it is infeasible to evaluate each element of the design space and evaluate it to all of the other ones. Heuristic search techniques may still be used resulting in suboptimal solution.

(b) in order to avoid that an heuristic search stops the search at a local top of the line, a 2nd approach referred to as random sampling is presented right here. It consists in determining randomly the couples of parameters however once more there isn't any guaranty to converge in opposition t a suitable result.

(c) With the guided-search approach, the dressmaker begins with a preliminary alternative of two parameters, and iterates around grade by grade except finding an appropriate trade-off. This approach avoids inconsistent or conflicting values for the different parameters and represents the best design solution when the entry factor is smartly chosen.

(d) Many other techniques could also be considered, as the use of genetic algorithms, computing device researching based mostly searches, etc.

For their design, they use the guided search of parameters. First, they assess essentially the most vital aspects of their architecture. Then, they use a design tool to quantify these distinctive facets and the rest of the architecture. So what they suggest here is a design methodology in line with a guided-search of parameters. The paper will proceed with the presentation of that design methodology, then the structure is specified. The results and the validation effects of the designed processor follow. and at last, further works are brought.

2. DESIGN METHODOLOGY

Our aim is to discover an excellent alternate-off between the time-todesign and the performances of an ASIP for a selected software domain.

2.1 Their benchmarks

For their case examine, they select the Audio and Speech requirements as a selected and generally used domain of embedded techniques. a few audio and speech standards with different encoding ideas are available, from lossless to lossy coding. desk 1 summarizes the set of benchmarks that they used for the Audio ASIP Design. almost all these benchmarks come from MediaBench. They cowl each distinct coding strategies and a few key points like bit-costs and computing complexities. extra particulars on audio coding techniques are given in [1], [2], [3] and [4].

desk 1: Audio purposes Benchmark

2.2 Benchmark Profiling and Analysing

The chosen benchmarks were profiled using GPROF [5], the public GNU profiler. The outputs of the profiler provide the call graphs and the hotspots, i.e. the most time ingesting functions. For their audio-speech benchmarks, they recognized 14 hotspot capabilities such as the codebook optimum parameters filter search from the CELP (Code Excited Linear Prediction) general or the MP3 (Mpeg-1 audio- half three- layer 3) Modified Discrete Cosine seriously change. these hotspots take over sixty six% of average execution time. With these evaluation of the hotspots, they cowl all audio wants. Their restricted number makes the manual analysis possible. The hotspots can also be analysed to verify the architectural points that might speed up the execution. as an instance, they are able to determine the register and storage wants, the records-route widths, and so on. as an instance, desk 2 gifts the number of registers that would be necessary for an effective execution of every audio-speech hotspot. These needs have been identified from the comparison of the life period of variables in the execution graph.

table 2: Estimated registers needs of audio-speech hotspots

we now have also recognized some particular code points that can be accelerated by using certain hardware facets reminiscent of a pre-arithmetic shift. Their benchmarks additionally intensively use loops for which optimizing both loop conditional branches and computation conditional branches is primary.

2.3 architecture Sizing

2.3.1 simple assumptions for the preliminary edition of the structure

The initial edition of the architecture that they used is now offered. It uses a customary RISC (decreased guideline- Set computer) instruction set architecture with 1-guideline delayed branches, conditional code flags (CC flags) for conditional branches (just like the SPARC ISA). The ISA (guide- Set architecture) is implemented both with a customary 5-stage pipeline for the scalar version and the n-manner superscalar or VLIW (Very lengthy instruction observe) types. Some points reduce the variety of completed guidance both for the scalar or n-means models. The number of CC flags is the sort of feature that is presented within the subsequent area. yet another basic function is the number of guidelines that the hardware can execute concurrently, i.e. the price of n for the n-way strategy. It can be mentioned in a subsequent part.

2.three.2 Conditional Codes Flags Sizing

As previously mentioned, loops are common in their benchmarks and they mix a loop branch and one (or a few) computation branch inside the loop. generally, the outcome of an entire loop computation is scaled on the end of the loop. So they need a flag for the loop branch and another one for the conditional influence scaling. Having one or a couple of CC flags influences on the typical efficiency of the loop.

desk three: comparison of Conditional Codes Flags Implementation

within the illustration shown within the desk three, implementing two diverse CC flags saves one cycle by means of loop iteration. With only 1 CC flag, there isn't any solution to replenish the extend slot after the loop branch, because the CMOV guide should follow the first SUBCC while the JMP CC must follow the 2d example of the SUBCC. With two different CC flags, the CMOV instruction will also be moved into the branch delay slot putting off the NOP that became obligatory within the previous case.

The benefit can rapidly grows with n-way architectures. in this circumstance, the loop department circumstance SUBCC1 may also be evaluated in the identical cycle as one other guideline. In desk four, with a 2-method structure, they save one more cycle per iteration.

desk 4: comparison of Conditional Codes Flags Implementation for a 2-ILP architecture

The have an impact on of the variety of CC flags can also be evaluated by way of a metric known as ”guide utilization price (IUR)”, it's described as the number of helpful guidance over the normal variety of guidelines (that contains useful and NOP guidance). This guide utilization expense can also be defined as 1−NOPpercentage. In table four, if the first M guidelines perfectly geared up on the structure leading to N/2 cycles and 0 NOP, an comparison of that metric for each implementations ends up in:

the use of a number of conditional codes flags increases the performance and it greater correctly uses the capabilities of the architecture. The chip area charge is comparatively small and there's no concern for the guideline-set coding. undoubtedly, the results that are proven in desk four are in line with a simple 5-stage pipeline like the MIPS-R2000 one [6]. Deeper pipelines could lead to other outcomes. for example, the pipeline of Alpha 21164 [7] had 2 execution degrees (EX1 and EX2): the evaluation of the situation turned into accomplished all over EX1 stage, whereas the conditional department become done all the way through EX2. in that case, each the guideline setting the condition and the conditional department can be scheduled in the same clock cycle casting off loads of NOP instructions in table four. the use of deeper pipelines may be considered in extra works.

2.3.three N-manner architectures

The aim of the article is to existing a design methodology in line with a driving parameter well chosen. They focal point on the variety of executions to be completed simultaneously because the using parameter. The leading goal to discover the most desirable architecture it is able to exploit the ILP (guide level Parallelism) that exists in the benchmarks with the minimal set of substances, i.e. the most reliable silicon efficiency.

We need to find the most beneficial triplet n-means (Nbways), instruction utilization fee (Tuse) and chip enviornment. The processor frequency and the resulting Nbop/sec are derived from the design for each distinct n-approach structure.

As no compiler is purchasable for every evaluated architecture, the most effective strategy to find the optimum triplet n-way -guide utilization fee and chip area is to manually time table operations in execution kernels according to each architecture. The assembly code of the recognized hotspots has been written and the corresponding execution time (in clock cycles) in keeping with the facts dependencies and the guideline utilization quotes had been calculated for distinctive parallel architectures (2, three, 4, 6 and eight-method architectures). They considered two types of data-paths : homogeneous information-paths have the same processing resources while heterogeneous architectures have selected processing materials for every means of the information-route.

For their audio-speech benchmarks, on homogeneous records-paths, the instruction utilization rate is 87% for a 2-approach VLIW, 74% for 3-manner, fifty four% for 4-way and fewer than 36% for wider architectures. most likely, the hotspot loops of the audio applications haven't adequate ILP to successfully make the most 6 or eight-means architectures. The guideline utilization rate on heterogeneous architectures is 87% for a 2-way, seventy two% for three-way and fifty two% for 4-manner architectures, as proven in determine 2.

Heterogeneous records-paths enable an important structure area shop. at the equal time, the utilization charges of each homogeneous and heterogeneous records-paths are fairly identical. So, coping with silicon effectivity because the leading metric, the use of parallel architectures with heterogeneous processing elements is terribly wonderful. they will best believe heterogeneous 2, three and four-approach architectures within the relaxation of the paper.

figure 2: guide utilization prices for n-way architectures for audio benchmarks

The 2nd step is to select the volume of parallelism in the architecture. This step needs a prediction of the evolution of the hardware complexity when duplicating supplies. From a RISC processor measurement distribution, they estimate the chip area of each parallel architectures according to here speculation :

  • The decoder hardware complexity is about 5% of the normal chip area.
  • The fetch cost is additionally about 5%.
  • The chip enviornment of a register file of 32 32-bit registers is about 35%.
  • The execution contraptions are imagined to use 40% of the typical area.
  • The closing 15% are assumed for the ultimate ingredients of the pipeline with its communique mechanisms and pipeline registers.
  • The evolution of the hardware complexity of different architectural features is also estimated. for instance, they agree with that the program reminiscence entry can charge is proportional to the number of fetched guidance per clock cycle. When n raises with n-means architectures, the decoder complexity raises, however many operations have mutual decoding. as a result, they assume that the decoder area raises proportionally to the rectangular root of the cost n. Bypassing and conversation mechanisms are additionally assumed to increase in response to the equal legislation.

    as the register file and the execution gadgets symbolize around three/four of the normal chip enviornment, they made some specific investigations to estimate more precisely their evolution when n increases. For the register file, a group of gate stage synthesis according to 2R/1W RF description has been finished. This look at shows a rise of 50% when doubling the variety of RF ports, a rise of one hundred% with a 6R/3W RF and over 2.5 enhance element for an 8R/4W RF versus the fashioned 2R/1W one. In table 5, they latest the hardware complexity evolution of n-method processors highly to the RISC area complexity.

    table 5: Hardware complexity evolution for n-method architectures with heterogeneous data-paths exceedingly to RISC processor

    Having evaluated each of the parameter introduced in the equation three, they will consider the distinctive n-approach architectures versus the scalar implementation (i.e. bypassing the Nbop/sec that is not already established). 4 their look at case, 2 and 3-method architectures characterize a pretty good trade-off for audio-speech applications.

    2.four building tool

    The Synopsys Processor clothier [8] is an automatic design device from the ADL (structure Description Language) LISA 2.0. It allows a good design comments to debug and optimize the structure. From a behavioral description of the operations, a number of architectures (RISC, DSP, VLIW) can also be implemented. additionally, an structure debugger offers a total visibility of the parameters at the execution time : registers, contents of the distinct recollections, guideline opcodes, pipeline stages, stalls and flushes, loop iterations, present pipeline alerts, and so forth. It permits a micro-step execution of the LISA guidelines, this is neither cycle-accurate nor instruction-correct however ”LISA-line-accurate”.

    This tool is used to dimension a design criteria and to hastily consider its have an effect on on the leading device. The development flow and the tool points used are presented in figure three. From the beginning aspect described in the past, this tool is used all through the guided search technique described in determine 1,c) of the part 1.

    determine 3: Audio Processor Design with Synopsys

    3. architecture OVERVIEW

    A block diagram of the designed processor is offered in figure 4.

    This figure shows a 5 pipeline stage architecture: instruction Fetch (FE), Decoding (DE), Execution (EX), memory or 2nd execution stage (MEM) and RF Writeback (WB). A n-approach constitution with three separate statistics-paths. The distribution of the operators with the aid of data-path changed into obtained from the functions evaluation and their computational patterns. The instruction utilization cost estimated gives a top level view of the rightness of the option. This distribution is given beneath :

  • statistics-path 1 : Arithmetic and common sense Unit, Jumps and Branches, and a 16x16!32-bit Multiplier.
  • data-direction 2 : Arithmetic Unit with CC Flags edition and a Shifter.
  • statistics-route three : ALU, Load/shop Unit, facts Manipulation (together with Conditional Writes).
  • All these facts-paths are 32-bit signed apart from the multiplication. The multiplier takes 16-bit operands and explicits signs with a view to help wider utility (un)signed multiplications. The 16x16!32-bit multiplication is performed within the MEM (or EX2) stage with a purpose to no longer lengthen its important direction (i.e. processor crucial direction) with the information hazard decision. The multiplier outcomes can be used within one cycle latency. The guideline-set coding is ninety six-bit broad with certainly two supply operands and one register effect (Opcodedestreg, src1reg, src2reg−or−imm). The 2nd operand may also be a register or an immediate cost usually 14- bit large. The Register File includes 32 32-bit registers. it is thoroughly attainable through the three records-paths: it includes 6 read and 3 Write ports. The branch and bounce unit is not represented during this determine. The corresponding guidelines are implemented by means of the decoder and the effect is given lower back to the fetch stage. Branches and jumps are delayed by one clock cycle, which skill that the lengthen slot have to be crammed by means of a constructive guide or a NOP. Like already presented within the illustration of Conditional Codes Flag Implementation, a conditional circulate is carried out, that both writes first or 2d operand to a register price in accordance with the state of CC flags. This approach replaces conditional branches by means of conditional transfers. Its utilization raises performances on account of availability of facts-paths and liberating situation comparison ready. the load/shop Unit makes it possible for records memory access. It has 4 entry modes : ”.W” to control notice-type statistics, ”.H” for signed half-note-huge facts, ”.UH” for equal broad unsigned one and ”.B” for eight-bit one. All these entry are done within the MEM stage which implies one cycle latency to make use of the loaded results.

    determine 4: architecture Overview

    4. outcomes AND VALIDATION

    4.1 structure Design

    The designed 3-method VLIW ASIP VHDL RTL has been generated using the Synopsys Processor dressmaker tool. RTL has next be gate-degree synthesized using Design Compiler from Synopsys targeting sixty five-nm Low vigor TSMC know-how. beneath a minimal time constraint of two.8ns, the normal chip enviornment is set 0.07mm2 with greater than forty five% committed to the Register File and 13% to the decoder. The validation technique consists in executing the profiled functions and evaluating the processor performances in terms of Silicon effectivity. determine 5 summarizes the universal design stream from the application benchmarks to the ASIP performance contrast.

    figure 5: Methodology Design stream

    First, they opt for a group of benchmarks from the application domain that they profile and analyze. Then, they look for the optimum triplet number of instructions carried out in parallel - guideline utilization rate and chip area. For this, they check how the meeting code of the distinct benchmark kernels execute on every n-manner structure and they consider the execution time and the guide utilisation rate. Third, they use a design tool to size a good processor. They iterate the technique except they meet their necessities. eventually, they validate the designed processor with a gate-level synthesis and they execute the studied hotspots kernels.

    As no compiler changed into accessible, the assembly code of three hotspots became manually-written and optimized to validate the ASIP structure. The hotspots of the profiled applications have been carried out on the processor leading to an instruction utilization price of 86%. They note that best three of the 14 hotspot functions were manually-written to consider their processor. They handiest represents about 20% of the average execution time. The Silicon effectivity of a processor is given by:

    The silicon effectivity of the designed ASIP is then:

    The designed three-way processor provides about 13GOPS/mm2. The development lasted a couple of months. Its clock velocity is about 357MHz and it executes efficiently GSM (international system for cellular communications), CELP, ADPCM (Adaptive Differential Pulse Code Modulation) and MP3 purposes.

    four.2 performance analysis

    The Synopsys Processor dressmaker permits a fast era of alternative Audio ASIP versions in keeping with the designed one. The purpose to the offered design methodology is to show that the design parameters have been appropriately sized. A small change of one of them leads to totally distinct outcomes. In an illustration before, they confirmed the impact of imposing two different conditional codes flags. Now they agree with the influence of smaller instructions.

    Few modifications are achieved to the ADL description to design 2-way VLIW and RISC implementations. Evaluating their performance with the audio benchmarks leads to diverse effects in silicon efficiency as presented in determine 6.

    figure 6: Normalized silicon efficiencies done by way of different n-means processors

    For the three evaluated hotspot functions, they obviously have a look at that n-manner architectures are more suitable than scalar ones. at the beginning of the study, taking simplest these 3 hotspots, three-approach structure turned into 0.78 times less productive than the 2-approach one in terms on Silicon efficiency. but for all the hostpots, the two models were quite an identical. The effects given in the determine 6 after implementation refer most effective to the execution of the three hotspots. So if they anticipate that the evolution from the preliminary consequences to the results after implementation will be the identical for all of the hotspot features, then they are expecting that the 3-means processor can be 1.23 times more desirable than the 2-means one and even more versus the scalar implementation.

    SPARC v8 is an guideline-set for RISC processors including load/store, arithmetic, logic and shift guidelines and the entire essential stuff for executing a big quantity of applications. They select the Leon3 implementation of the SPARC v8 ISA to be their referent for the ASIP performance done. The Leon3 has a seven stage pipeline with a Harvard structure (with separated program and data reminiscences). It comprises a hardware multiplier/divider and a three-port Register File. The particular register file includes 32 registers organized in home windows. The three validation capabilities are finished on it and its RTL implementation is gate degree synthesized with the equal Low-vigor TSMC library. The basic design dimension is about 0.035mm2 with a clock velocity of 357MHz. In desk 6 they examine each the results of the designed three-means ASIP and the consequences of the Leon3 processor executing the audio functions. With the described design methodology, the audio-speech 3-method ASIP is set 70% more productive than the Leon3 processor.

    desk 6: Audio ASIP vs Leon3 Silicon Efficiencies

    5. CONCLUSION AND FUTURE WORK

    The applied methodology allowed a fast Design area Exploration and an effective sizing of the important thing parameters. Their methodology has a couple of barriers:

  • Manually assembly coding a whole benchmark can’t be achieved to opt for the appropriate structure sizing. within the audio example, they modeled over sixty six% of the set of their benchmarks. This leads us to the option of a 3-approach structure, however they have no warranty that the remaining 34% would no longer regulate this alternative.
  • Predicting the evolution of complexity can hardly ever be carried out if they are faced to advanced system designs with hierarchical recollections and sophisticated community connections.
  • The designed VLIW ASIP became very efficient in terms of efficiency. but its Silicon effectivity become badly decreased by means of its chip enviornment. They noticed that the Register File took over forty five% of the general area. In future works, they will focal point on cutting back the standard system silicon charge.

    REFERENCES

    [1] Karlheinz Brandenburg, Oliver Kunz, and Akihiko Sugiyama. Mpeg-4 herbal audio coding. signal Processing: graphic verbal exchange, 15:423–444, 2000.

    [2] M. Budagavi and J.D. Gibson. Speech coding in cell radio communications. proceedings of the IEEE, 86(7):1402–1412, July 1998.

    [3] Andres Vega Garcia. M´ecanismes de controle pour la transmission de l’audio sur l’information superhighway. PhD thesis, fine- Sophia Antipolis institution, October 1996.

    [4] A.S. Spanias. Speech coding: an instructional evaluation. court cases of the IEEE, eighty two(10):1541–1582, October 1994.

    [5] http://www.ibm.com/developerworks/linux/library/lgnuprof.html?ca=dgr-lnxw02gnuprofiler.

    [6] N. Pinckney, T. Barr, M. Dayringer, M. McKnett, Nan Jiang, C. Nygaard, D. funds Harris, J. Stanley, and B. Phillips. A mips r2000 implementation. pages 102– 107, June 2008.

    [7] P. Bannon and J. Keller. inside structure of alpha 21164 microprocessor. In Compcon ’ninety five.’technologies for the tips Superhighway’, Digest of Papers., pages seventy nine–87, Mar 1995.

    [8] Karl V. Rompaey, Diederik Verkest, Ivo Bolsens, and Hugo D. Man. Coware - a design ambiance for heterogeneous hardware/utility systems. EURO-DAC, pages 252–257, 1996.




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